Zhuolun (Leon) HE

Postdoctoral Fellow
Department of Computer Science and Engineering
The Chinese University of Hong Kong

Co-Founder & CEO
ChatEDA Tech

B.Sc. (Peking U) Ph.D. (CUHK)
[zleonhe at gmail dot com] [CV] [Google Scholar]

I am a postdoctoral researcher at the Department of Computer Science and Engineering, Chinese University of Hong Kong, and the co-founder & CEO of ChatEDA Tech. I received my Ph.D. degree from CUHK in 2023, supervised by Prof. Bei Yu, and my B.Sc. degree from Peking University in 2017. I received the Best Paper Award Nomination from International Conference on Computer-Aided Design (ICCAD) 2024, the Best Paper Award Nomination from International Symposium on Physical Design (ISPD) 2024, championship of EDAthon 2018, and the 3rd place in ISPD contest 2020.

Research summary:

  • LLM empowered EDA (MLCAD'23, ISPD'24, TCAD'24, ICCAD'24)
  • Efficient physical verification (ICCAD'22, DATE'23, DAC'23, ICCAD'23, DAC'24)
  • Netlist representation learning (ISPD'20, ICCAD'21, DAC'22, TCAD'23, TCAD'24)
  • Physical design for neural processor (ASPDAC'21, 3rd place in ISPD contest 2020)
  • Reinforcement learning driven physical synthesis (ICCD'20, ICSICT'20)
  • Heterogeneous accelerator design (FPGA'17, FCCM'18, TCAD'23)

    2025

  1. Jiahao Xu, Zhuolun He, Shuo Yin, Yuan Pu, Wenjian Yu, and Bei Yu. "EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling," ACM Transactions on Design Automation of Electronic Systems (TODAES), 2025.

  2. Siting Liu, Jieya Zhou, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, and Martin Wong. "Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs," ACM Transactions on Design Automation of Electronic Systems (TODAES), 2025.

  3. Haisheng Zheng, Haoyuan Wu, and Zhuolun He. "ChatLS: Multimodal Retrieval-Augmented Generation and Chain-of-Thought for Logic Synthesis Script Customization," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 22–25, 2025.

  4. Hang Liu, Hao Geng, Zhuolun He, Qi Sun, and Cheng Zhuo. "Swift or Exact? Boosting Efficient Microarchitecture DSE via Multi-fidelity Partial Order Prediction," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 22–25, 2025.

  5. Haoyuan Wu, Haisheng Zheng, Zhuolun He, and Bei Yu. "Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automation," Nations of the Americas Chapter of the Association for Computational Linguistics (NAACL), Albuquerque, NM, USA, Apr. 29–May. 04, 2025.

  6. Yuan Pu, Tinghuan Chen, Zhuolun He, Jiajun Qin, Chen Bai, Haisheng Zheng, Yibo Lin, and Bei Yu. " IncreMacro: Incremental Macro Placement Refinement," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.

  7. Zhuolun He, Yuan Pu, Haoyuan Wu, Yuhan Qin, Tairu Qiu, and Bei Yu. "Large Language Models for EDA: From Assistants to Agents," Foundations and Trends in Electronic Design Automation, 2025.

  8. Haisheng Zheng, Haoyuan Wu, Zhuolun He, Yuzhe Ma, and Bei Yu. "iRw: An Intelligent Rewriting," IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Lyon, France, Mar. 31–Apr. 02, 2025.

  9. Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, and Bei Yu. "HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning," ACM International Symposium on Physical Design (ISPD), Austin, IL, USA, Mar. 16–19, 2025. (Best Paper Award Nomination) [Paper]

  10. Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Yu Huang, and Bei Yu. " FGNN2: A Powerful Pre-training Framework for Learning the Logic Functionality of Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025. [Paper] [Code]

    11. 2024

  11. Haoyuan Wu, Haisheng Zheng, Zhuolun He, and Bei Yu. " Parameter-Efficient Sparsity Crafting from Dense to Mixture-of-Experts for Instruction Tuning on General Tasks," Empirical Methods in Natural Language Processing (EMNLP), Miami, FL, USA, Dec. 12-16, 2024. [Paper] [Poster] [Slides]

  12. Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, and Bei Yu. "Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Newark, NJ, USA, Oct. 27-31, 2024. (Best Paper Award Nomination) [Paper] [Slides]

  13. Haoyuan Wu, Zhuolun He, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, and Bei Yu. " ChatEDA: A Large Language Model Powered Autonomous Agent for EDA," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024. [Paper]

  14. Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Kai-Yuan Chao, Yibo Lin, and Bei Yu. " Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 23–27, 2024. [Paper] [Slides]

  15. Jiaxi Jiang, Lancheng Zou, Wenqian Zhao, Zhuolun He, Tinghuan Chen, Bei Yu. " PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan Geometry," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 23–27, 2024. [Paper] [Slides]

  16. Fangzhou Liu, Zehua Pei, Ziyang Yu, Haisheng Zheng, Zhuolun He, Tinghuan Chen, and Bei Yu. “ CBTune: Contextual Bandit Tuning for Logic Synthesis,” IEEE/ACM Design, Automation and Test in Europe Conference (DATE), Valencia, Spain, Mar. 25–27, 2024. [Paper] [Slides] [Poster]

  17. Zhuolun He, and Bei Yu. “ Large Language Models for EDA: Future or Mirage?,” ACM International Symposium on Physical Design (ISPD), Taipei, Mar. 12–15, 2024. [Paper]

  18. Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, and Bei Yu. " IncreMacro: Incremental Macro Placement Refinement," ACM International Symposium on Physical Design (ISPD), Taipei, Mar. 12–15, 2024. (Best Paper Award Nomination) [Paper] [Slides]

  19. Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, and Bei Yu. “ Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs,” ACM International Symposium on Physical Design (ISPD), Taipei, Mar. 12–15, 2024. [Paper] [Slides]

  20. Haisheng Zheng, Zhuolun He, Fangzhou Liu, Zehua Pei, and Bei Yu. “ A Logic Synthesis Timing Predictor,” IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Incheon, South Korea, Jan. 22–25, 2024. [Paper] [Slides]

    21. 2023

  21. Zhuolun He, and Bei Yu. “ Heterogenous Acceleration for Design Rule Checking,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, USA, Oct. 29-Nov. 2, 2023. (Invited Paper) [Paper] [Slides]

  22. Zehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu, and Bei Yu. “ AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, USA, Oct. 29-Nov. 2, 2023. [Paper] [Slides] [Poster]

  23. Zhuolun He, Haoyuan Wu, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, and Bei Yu. “ ChatEDA: A Large Language Model Powered Autonomous Agent for EDA,” ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), Snowbird, UT, USA, Oct. 29–Nov. 2, 2023. [Paper] [arXiv]

  24. Zhuolun He, Yihang Zuo, Jiaxi Jiang, Haisheng Zheng, Yuzhe Ma, and Bei Yu. “ OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration,” ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, July 9-13, 2023. [Paper] [Slides]

  25. Zehua Pei, Wenqian Zhao, Zhuolun He, and Bei Yu. “ Quantization for Efficient Layout Hotspot Detection,” International Symposium of Electronics Design Automation (ISEDA), Nanjing, China, May 9–11, 2023. [Paper]

  26. Bizhao Shi, Jiaxi Zhang, Zhuolun He, Xuechao Wei, Sicheng Li, Guojie Luo, Hongzhong Zheng, and Yuan Xie. “ Efficient Super-Resolution System with Block-wise Hybridization and Quantized Winograd on FPGA,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.

  27. Ziyi Wang, Zhuolun He, Chen Bai, Haoyu Yang, and Bei Yu. “ Efficient Arithmetic Block Identification with Graph Learning and Network-flow,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.

  28. Wei Zhong, Zhenhua Feng, Zhuolun He, Weimin Wang, Yuzhe Ma, and Bei Yu. “ Enabling Efficient Design Rule Checking with GPU Acceleration,” IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Antwerp, Belgium, Apr. 17-19, 2023. (extended abstract) [Paper]

  29. Yuxuan Zhao, Qi Sun, Zhuolun He, Yang Bai, and Bei Yu. “ Optimizing DNN Computation Graph for Parallel GPU Kernel Execution,” AAAI Conference on Artificial Intelligence (AAAI), Washington, DC, USA, Feb. 7-14, 2023. [Paper] [Slides]

    30. 2022

  30. Zhuolun He, Yuzhe Ma, and Bei Yu. “ X-Check: GPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Diego, CA, USA, Oct. 30-Nov. 3, 2022. [Paper] [Slides]

  31. Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, and Yu Huang. “ Functionality Matters in Netlist Representation Learning,” ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, July 10-14, 2022. [Paper] [Slides]

    32. 2021

  32. Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, and Bei Yu. “ Graph Learning-Based Arithmetic Block Identification,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Germany, Nov. 1-4, 2021. [Paper] [Slides]

  33. Zhuolun He, Peiyu Liao, Siting Liu, Yuzhe Ma, and Bei Yu. “ Physical Synthesis for Advanced Neural Network Processors,” IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan. 18-21, 2021. (Invited Paper) [Paper] [Slides]

    34. 2020

  34. Zhuolun He, Lu Zhang, Peiyu Liao, Yuzhe Ma, and Bei Yu. “ Reinforcement Learning Driven Physical Synthesis,” IEEE International Conference on Solid -State and Integrated Circuit Technology (ICSICT), Kunming, China, Nov. 3-6, 2020. (Invited Paper) [Paper]

  35. Rui Lin, Ching-Yun Ko, Zhuolun He, Cong Chen, Yuan Cheng, Hao Yu, Graziano Chesi, and Ngai Wong. “ HOTCAKE: Higher Order Tucker Articulated Kernels for Deeper CNN Compression,” IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), China, Nov. 3-6, 2020. (Invited Paper) [Paper]

  36. Zhuolun He, Yuzhe Ma, Lu Zhang, Peiyu Liao, Ngai Wong, Bei Yu, and Martin D. F. Wong. “ Learn to Floorplan through Acquisition of Effective Local Search Heuristics,” IEEE International Conference on Computer Design (ICCD), Hartford, CT, USA, Oct. 18-21, 2020. [Paper] [Slides]

  37. Yuzhe Ma, Zhuolun He, Wei Li, Tinghuan Chen, Lu Zhang, and Bei Yu. “ Understanding Graphs in EDA: From Shallow to Deep Learning,” ACM International Symposium on Physical Design (ISPD), Taipei, Mar. 25-Apr. 1, 2020. (Invited Paper) [Paper]

    38. 2019

  38. Ching-Yun Ko, Cong Chen, Zhuolun He, Yuke Zhang, Kim Batselier, and Ngai Wong. “ Deep Model Compression and Inference Speedup of Sum-Product Networks on Tensor Trains,” IEEE Transactions on Neural Networks and Learning Systems (TNNLS), 2019.

    39. 2018

  39. Zhuolun He, Hanxian Huang, Ming Jiang, Yuanchao Bai, and Guojie Luo. “ FPGA-based Real-time Super-resolution System for Ultra High Definition Videos,” IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boulder, CO, USA, Apr. 29-May. 1, 2018. [Paper] [Slides]

    40. 2017

  40. Zhuolun He and Guojie Luo. “ FPGA Acceleration for Computational Glass-Free Displays,” ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, USA, Feb. 22-24, 2017. [Paper] [Slides]