Zhuolun (Leon) HE

[zleonhe at gmail dot com] [CV] [Google Scholar]

I am a postdoctoral fellow at the Department of Computer Science and Engineering, Chinese University of Hong Kong, supervised by Prof. Bei Yu.
B.Sc. (Peking U) Ph.D. (CUHK)

Research summary:

Publication

  1. Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Kai-Yuan Chao, Yibo Lin, and Bei Yu. “Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs,” ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 23–27, 2024.

  2. Jiaxi Jiang, Lancheng Zou, Wenqian Zhao, Zhuolun He, Tinghuan Chen, Bei Yu. “PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan Geometry,” ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 23–27, 2024.

  3. Fangzhou Liu, Zehua Pei, Ziyang Yu, Haisheng Zheng, Zhuolun He, Tinghuan Chen, and Bei Yu. “CBTune: Contextual Bandit Tuning for Logic Synthesis,” IEEE/ACM Design, Automation and Test in Europe Conference (DATE), Valencia, Spain, Mar. 25–27, 2023.

  4. Zhuolun He, and Bei Yu. “Large Language Models for EDA: Future or Mirage?,” ACM International Symposium on Physical Design (ISPD), Taipei, Mar. 12–15, 2024. [Paper]

  5. Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, and Bei Yu. “IncreMacro: Incremental Macro Placement Refinement,” ACM International Symposium on Physical Design (ISPD), Taipei, Mar. 12–15, 2024. (Best Paper Award Nomination) [Paper]

  6. Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, and Bei Yu. “Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs,” ACM International Symposium on Physical Design (ISPD), Taipei, Mar. 12–15, 2024. [Paper]

  7. Haisheng Zheng, Zhuolun He, Fangzhou Liu, Zehua Pei, and Bei Yu. “LSTP: A Logic Synthesis Timing Predictor,” IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Incheon, South Korea, Jan. 22–25, 2024. [Paper] [Slides]

  8. Zhuolun He, and Bei Yu. “ Heterogenous Acceleration for Design Rule Checking,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, USA, Oct. 29-Nov. 2, 2023. (Invited Paper) [Paper] [Slides]

  9. Zehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu, and Bei Yu. “ AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, USA, Oct. 29-Nov. 2, 2023. [Paper] [Slides] [Poster]

  10. Zhuolun He, Haoyuan Wu, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, and Bei Yu. “ ChatEDA: A Large Language Model Powered Autonomous Agent for EDA,” ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), Snowbird, UT, USA, Oct. 29–Nov. 2, 2023. [Paper] [arXiv]

  11. Zhuolun He, Yihang Zuo, Jiaxi Jiang, Haisheng Zheng, Yuzhe Ma, and Bei Yu. “ OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration,” ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, July 9-13, 2023. [Paper] [Slides]

  12. Zehua Pei, Wenqian Zhao, Zhuolun He, and Bei Yu. “ Quantization for Efficient Layout Hotspot Detection,” International Symposium of Electronics Design Automation (ISEDA), Nanjing, China, May 9–11, 2023. [Paper]

  13. Bizhao Shi, Jiaxi Zhang, Zhuolun He, Xuechao Wei, Sicheng Li, Guojie Luo, Hongzhong Zheng, and Yuan Xie. “ Efficient Super-Resolution System with Block-wise Hybridization and Quantized Winograd on FPGA,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.

  14. Ziyi Wang, Zhuolun He, Chen Bai, Haoyu Yang, and Bei Yu. “ Efficient Arithmetic Block Identification with Graph Learning and Network-flow,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.

  15. Wei Zhong, Zhenhua Feng, Zhuolun He, Weimin Wang, Yuzhe Ma, and Bei Yu. “ Enabling Efficient Design Rule Checking with GPU Acceleration,” IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Antwerp, Belgium, Apr. 17-19, 2023. (extended abstract) [Paper]

  16. Yuxuan Zhao, Qi Sun, Zhuolun He, Yang Bai, and Bei Yu. “ Optimizing DNN Computation Graph for Parallel GPU Kernel Execution,” AAAI Conference on Artificial Intelligence (AAAI), Washington, DC, USA, Feb. 7-14, 2023. [Paper] [Slides]

  17. Zhuolun He, Yuzhe Ma, and Bei Yu. “ X-Check: GPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Diego, CA, USA, Oct. 30-Nov. 3, 2022. [Paper] [Slides]

  18. Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, and Yu Huang. “ Functionality Matters in Netlist Representation Learning,” ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, July 10-14, 2022. [Paper] [Slides]

  19. Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, and Bei Yu. “ Graph Learning-Based Arithmetic Block Identification,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Germany, Nov. 1-4, 2021. [Paper] [Slides]

  20. Zhuolun He, Peiyu Liao, Siting Liu, Yuzhe Ma, and Bei Yu. “ Physical Synthesis for Advanced Neural Network Processors,” IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan. 18-21, 2021. (Invited Paper) [Paper] [Slides]

  21. Zhuolun He, Lu Zhang, Peiyu Liao, Yuzhe Ma, and Bei Yu. “ Reinforcement Learning Driven Physical Synthesis,” IEEE International Conference on Solid -State and Integrated Circuit Technology (ICSICT), Kunming, China, Nov. 3-6, 2020. (Invited Paper) [Paper]

  22. Rui Lin, Ching-Yun Ko, Zhuolun He, Cong Chen, Yuan Cheng, Hao Yu, Graziano Chesi, and Ngai Wong. “ HOTCAKE: Higher Order Tucker Articulated Kernels for Deeper CNN Compression,” IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), China, Nov. 3-6, 2020. (Invited Paper) [Paper]

  23. Zhuolun He, Yuzhe Ma, Lu Zhang, Peiyu Liao, Ngai Wong, Bei Yu, and Martin D. F. Wong. “ Learn to Floorplan through Acquisition of Effective Local Search Heuristics,” IEEE International Conference on Computer Design (ICCD), Hartford, CT, USA, Oct. 18-21, 2020. [Paper] [Slides]

  24. Yuzhe Ma, Zhuolun He, Wei Li, Tinghuan Chen, Lu Zhang, and Bei Yu. “ Understanding Graphs in EDA: From Shallow to Deep Learning,” ACM International Symposium on Physical Design (ISPD), Taipei, Mar. 25-Apr. 1, 2020. (Invited Paper) [Paper]

  25. Ching-Yun Ko, Cong Chen, Zhuolun He, Yuke Zhang, Kim Batselier, and Ngai Wong. “ Deep Model Compression and Inference Speedup of Sum-Product Networks on Tensor Trains,” IEEE Transactions on Neural Networks and Learning Systems (TNNLS), 2019.

  26. Zhuolun He, Hanxian Huang, Ming Jiang, Yuanchao Bai, and Guojie Luo. “ FPGA-based Real-time Super-resolution System for Ultra High Definition Videos,” IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boulder, CO, USA, Apr. 29-May. 1, 2018. [Paper] [Slides]

  27. Zhuolun He and Guojie Luo. “ FPGA Acceleration for Computational Glass-Free Displays,” ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, USA, Feb. 22-24, 2017. [Paper] [Slides]

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